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Incremental placement for layout driven optimizations on FPGAs
2002
Computer-Aided Design (ICCAD), IEEE International Conference on
This paper presents an algorithm to update the placement of logic elements when given an incremental netlist change. Specifically, these algorithms are targeted to incrementally place logic elements created by layout-driven circuit restructuring techniques. The incremental placement engine assumes that the restructuring algorithms provide a list of new logic elements along with preferred locations for each of these new elements. It then tries to shift non-critical logic elements in the original
doi:10.1145/774572.774683
dblp:conf/iccad/SinghB02
fatcat:ioual4yf5jfwni7jv6b5kpsdpe