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Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.
We propose an integrated architectural/physical planning approach to reduce the power supply noise due to current surge in high performance, general-purpose, clock-gated microprocessors. The proposed approach combines dynamic selection of functional units on-the-fly, dynamic issue width scaling and physical planning with soft module, to balance the current demand across layout. Experimental results show that the proposed approach could reduce the peak noise by 6.54% and consequently, thedoi:10.1109/lpe.2003.1231867 fatcat:vazrvit5gfh2hgtnud4j3fwdvi