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A Systolic LLR Generation Architecture for Non-Binary LDPC Decoders
2011
IEEE Communications Letters
Non-Binary LDPC codes offer higher performances than their binary counterpart but suffer from higher decoding complexity. A solution to reduce the decoding complexity is the use of the Extended Min-Sum algorithm. The first step of this algorithm requires the generation of the first n m largest Log-Likelihood Ratio (LLR), sorted in increasing order, of each received symbol. In the case where GF(q) symbols are transmitted using a BPSK modulation, we propose a simple systolic architecture that generates the sorted list of symbols.
doi:10.1109/lcomm.2011.061611.110268
fatcat:t2y43qipg5gjzodydg4ubdtply