Phase-locked coherent optical interconnects for data links

M. J. W. Rodwell, H. C. Park, M. Piels, M. Lu, D. Elias, A. Sivananthan, E. Bloch, Z. Griffith, L. Johansson, J. E. Bowers, L. A. Coldren
2014 2014 Optical Interconnects Conference  
In large-scale digital systems, propagation delay and power consumption of the interconnects are vastly larger than that of the transistors themselves [1, 2] . Reduced power consumption, and increased capacity is required for interconnects, whether on-chip, between circuit boards, or within large data centers. Here we will consider coherent optical interconnects for high-capacity, sub-km links within data centers. At the other extreme of interconnect length, we will also briefly consider
more » ... tive approaches for reduced CV 2 /2 switching energy of VLSI interconnects. Within data centers, optical links can readily provide >> 100 Gb/s capacity using wavelength-division and polarization multiplexing. Coherent links [3] offer more complex constellations, increased spectral efficiency, and greater capacity. Most long-haul coherent links [3] use free-running local oscillator (LO) lasers; the receiver uses digital signal processing (DSP) to both equalize dispersion and correct LO phase fluctuations. In few-km links, dispersion need not be compensated; if the LO laser is then phase-locked to the received signal, DSP can then be eliminated to greatly reduce receiver cost and DC power. In phase-locked [4, 5] coherent receivers, the LO laser phase is locked to the received signal. In optical PLLs (OPLLs) [6,7,8], wide ~1GHz loop bandwidths are necessary to suppress the LO laser's phase noise, and, as noted by Coldren [6,7,8] photonic integration (PIC) is required to provide the needed small component propagation delays. Because the signal and LO lasers may be initially offset by 5-50GHz, broadband (DC~50GHz) phase-frequency [9] difference detectors force the loop to lock. By these techniques we have demonstrated 35Gb/s coherent phase-locked BPSK receivers [6] (fig . 1a) . Used in WDM transmitters, OPLLs can further improve spectral efficiency. Using broadband digital SSB mixing [9], the OPLL forces a frequency offset of controlled sign between the reference and slave lasers, generating optical frequency offsets, and WDM channel separations, at the ~1 ppm. precision of a microwave synthesizer ( fig. 1b) . This is optical frequency synthesis. Cascading such offset OPLLs, precise WDM combs can be generated. In coherent receivers, WDM signals can be demultiplexed electrically [10] ( fig. 2) , replacing many WDM receivers with one PIC and one electrical IC. WDM signals at 25GHz separation become electrical subcarriers at 25GHz separation, and are downconverted to DC. There are large potential power-savings; initial demonstrations [10] used several-Watt ICs, but power can be saved using CMOS time-domain mixers [11] and charge-steering logic [12] . Today's ICs support 600 GHz bandwidths [13] , hence one such electrical IC might recover 48 WDM channels at 25 GHz channel spacing. On-chip interconnect CV DD 2 /2 dissipation is a central barrier to improved digital systems [1, 2] . Though tunnel FETs offer reduced V DD , projected I on is small [14] , hence logic will be slow. Alternatives to the widely-studied tunnel FET thus warrant greater consideration. By operating finFETs near threshold ( fig. 3 ) for low V DD and then increasing the fin heightspacing ratio [15, 16] to offset the loss in on-current arising from the low V DD , low CV DD 2 /2 dissipation, and moderately high drive current per unit IC area, hence low gate delay, can be obtained simultaneously. At the expense of two supplies and three PMOS thresholds, CV DD 2 /2 dissipation can also be reduced using circuit techniques with low-static-dissipation interconnect buffers with voltage gain (fig. 4) . Here long interconnects are driven by gates with a low V DD , producing a 200 mV swing. The interconnect receivers must have shifted V th to maintain low I off , hence have low I on . Buffer gate delay is minimized by using only short interconnects (<1 m) between the line receivers and normal 500-mV-V DD logic stages.
doi:10.1109/oic.2014.6886108 fatcat:euczbqsgkvbd5bmx4u4xfsnw7u