Design and Implementation of On Modulo 2 n +1 Adder Design Using FPGA

Srinivasa Ch, Raoand, Pavan Kumar
2013 International Journal of New Trends in Electronics and Communication (IJNTEC)   unpublished
Arithmetic modulo 2 n +1 has found applicability in a variety of fields ranging from pseudorandom number generation and cryptography up to convolution computations without round-off errors. Also, modulo 2 n +1 operator are commonly included in residue number system (RNS) applications. The RNS is an arithmetic system which decomposes a number into parts (residues) and performs arithmetic operations in parallel for each residue without depending on the propagation of previous carry bits, which
more » ... arry bits, which leads to decrease the delay of leading significant bits for binary operations. RNS is well appropriate to applications that are rich of arithmetic operations and has been adopted in the design of digital signal processors, FIR filters and communication devices offering in several cases apart from enhanced operation speed, low-power characteristics. The complexity of a modulo 2 n +1 arithmetic unit will be determine by 3 depictions, they are the normal weighted one, the diminished-1 and the signed-LSB representations .Only consider the first two representations in the subsequent, since the implementation of the signed-LSB representation does not lead to more efficient circuits in delay or area terms. By using two architectures, on modulo 2 n +1 adder has been developed. The first one is developed by using a sparse carry computation unit that computes only some of the carries of the on modulo 2 n +1 addition. This sparse approach is facilitated by the preface of the inverted circular idem potency property of the parallel-prefix carry operator and its regularity and area efficiency are improved by adding a new prefix operator. The ensuing diminished-1 adders can be developed in less area and use less power compared to all former proposal, while maintaining a high operation speed. The second one coalesce the design of modulo 2 n ± 1 adders. It is shown that modulo 2 n +1 adder can be easily derived by straightforward modifications of modulo 2 n-1 adder with minor hardware overhead