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Parallelizing DSP nested loops on reconfigurable architectures using data context switching
Proceedings of the 38th conference on Design automation - DAC '01
Recon gurable architectures promise signi cant performance and exibility advantages over conventional architectures. Automatic mapping techniques that exploit the features of the hardware are needed to leverage the power of these architectures. In this paper, we develop techniques for parallelizing nested loop computations from digital signal processing DSP applications onto high performance pipelined con gurations. We propose a novel data context switching technique that exploits the embeddeddoi:10.1145/378239.378483 dblp:conf/dac/Bondalapati01 fatcat:3sjpmx6xezhj7ijthcoz5ut2oa