Parallelizing DSP nested loops on reconfigurable architectures using data context switching

Kiran Bondalapati
2001 Proceedings of the 38th conference on Design automation - DAC '01  
Recon gurable architectures promise signi cant performance and exibility advantages over conventional architectures. Automatic mapping techniques that exploit the features of the hardware are needed to leverage the power of these architectures. In this paper, we develop techniques for parallelizing nested loop computations from digital signal processing DSP applications onto high performance pipelined con gurations. We propose a novel data context switching technique that exploits the embedded
more » ... istributed memory available in recon gurable architectures to parallelize such loops. Our technique is demonstrated on two diverse state-of-the-art recon gurable architectures, namely, Virtex and the Chameleon Systems Recon gurable Communications Processor. Our techniques show signi cant performance improvements on both architectures and also perform better than state-of-the-art DSP and microprocessor architectures.
doi:10.1145/378239.378483 dblp:conf/dac/Bondalapati01 fatcat:3sjpmx6xezhj7ijthcoz5ut2oa