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A Band-Reject Nested-PLL Clock Cleaner Using a Tunable MEMS Oscillator
2014
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
This paper presents the Band-Reject Nested-PLL (BRN-PLL) scheme that simultaneously improves filtering of a noisy input signal and relaxes the requirements for the loop bandwidth. As the architecture employs a modified PLL as a divider of another PLL, a stability analysis is presented to demonstrate suitable operation. The BRN-PLL close-to-carrier output noise is dominated by the PFD/CP of the inner PLL and the far-from-carrier output noise is dominated by the LO of the outer PLL. The PFD/CP
doi:10.1109/tcsi.2013.2284186
fatcat:gwlyg6lim5czld7pugbg4oycre