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A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures
2007
2007 IEEE 13th International Symposium on High Performance Computer Architecture
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On the other hand, chip-multiprocessors (CMP) that integrate several processor cores in a single chip are nowadays the best alternative to more efficient use of the increasing number of transistors that can be placed in a single die. Hence, it is necessary to design new techniques to deal with these faults to be able to
doi:10.1109/hpca.2007.346194
dblp:conf/hpca/PascualGAD07
fatcat:wovatyfofrajdmp7fv464kcgoe