Most behavioral synthesis and design for testability techniques target subsequent gate-level sequential test generation, which isfrequently incapable of handling complex controllerzdatapath circuits with large datapath bit-widths. Hierarchical testing attempts to counter the complexity of test generation by exploiting information from multiple levels of the design hierarchy. We present techniques that add minimal test hardware to the given register-transfer level (RTL) design obtained through

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... havioral synthesis in oiler to ensure that all the embedded modules in the circuit are hierarchically testable. An important by-product of our DFTprocedure is a system-level test set that is guaranteed to deliver pre-computed module test sets to each module in the RTL circuit. This eliminates the need to apply gate-level sequential test generation to the controller/data path. We peeormed extensive experiments with several complex data patWcontroller circuits synthesized by two different high-late1 synthesis systems which do not target testability. The key advantages of our method include: (i) the area and delay overheads incurred for testability are very low (the average area overhead was 3.15% and the average delay overhead was only 0.36%), (ii} both the DFT addition and test generation algorithms are independent of the data path bit-width (we generate test sets which have over 99% fault coverage in almost all the cases, in test generation times that are 2 to 4 orders of magnitude lower than current gate-level sequential test generators), and {iii) unlike methods that use scan, our system-level test sets can be applied at-speed.