Dealing with Aging and Yield in Scaled Technologies [chapter]

Wei Ye, Mohamed Baker Alawieh, Che-Lun Hsu, Yibo Lin, David Z. Pan
2020 Embedded Systems  
AbstractThis chapter reviews recent practices of tackling aging and yield issues in VLSI design related to shrinking technology processes. Different fundamental effects such as device aging, interconnect electromigration, and process variations are investigated with the state-of-the-art techniques for modeling and optimization. The presented techniques vary from analytical approaches to machine learning, and often require cross-layer information feedback for robust design cycles.
doi:10.1007/978-3-030-52017-5_17 fatcat:shivkxo2afchtexgievin4hotq