Fault-tolerant Architectures for Nanowire and Quantum Array Devices [article]

Tamer Mohamed, University Of Calgary, University Of Calgary, Svetlana Yanushkevich
2013
This work investigates techniques for building fault-tolerant digital circuits at the nano-scale. It provides an overview of some nano-scale technology candidates that can be used in the next generation of digital circuit based on nanoelectronic logic fabrics. It focuses on fault tolerance of such circuits at both the circuit and the architecture level. A case study based on pass-transistor logic using wrap-gate nanowire devices is presented. Such circuits implement logic computing in the form
more » ... f binary decision diagrams (BDDs), however, they are not fault-immune. In this thesis, the BDD based nanowire devices that incorporate error correction coding are proposed. In addition, a planarization algorithm is presented and implemented in order to synthesize planar error correcting circuits using such devices. Alternative architecture, such as the cross-bar nano-FPGA, is considered as another candidate for fault-tolerance. Simulation and modeling of all the presented architectures are performed using the developed software "BDD processing tool", CUDD package and SPICE.
doi:10.11575/prism/26166 fatcat:eaqzsejvsbachi33kkdavespsi