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Noise-aware repeater insertion and wire sizing for on-chip interconnect using hierarchical moment-matching
Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361)
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] a noiseaware repeater insertion technique has also been proposed recently. Recognizing the conservatism of these delay and noise models, we propose a moment-matching based technique to interconnect optimization that allows for much higher accuracy while preserving the hierarchical nature of Elmore-delay-based
doi:10.1109/dac.1999.781367
fatcat:vyhlji2u5vaojes3tgq6titi2i