A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2010; you can also visit the original URL.
The file type is
In this paper, two Static Random Access Memory (SRAM) cells that reduce the static power dissipation due to gate and sub-threshold leakage currents are presented. The first cell structure results in reduced gate voltages for the NMOS pass transistors, and thus lowers the gate leakage current. It reduces the subthreshold leakage current by increasing the ground level during the idle (inactive) mode. The second cell structure makes use of PMOS pass transistors to lower the gate leakage current.doi:10.1109/tvlsi.2008.2004590 fatcat:onpsyxeflfgvtjloo3qlyfgauu