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A new memory monitoring scheme for memory-aware scheduling and partitioning
Proceedings Eighth International Symposium on High Performance Computer Architecture
We propose a low overhead, on-line memory monitoring scheme utilizing a set of novel hardware counters. The counters indicate the marginal gain in cache hits as the size of the cache is increased, which gives the cache miss-rate as a function of cache size. Using the counters, we describe a scheme that enables an accurate estimate of the isolated miss-rates of each process as a function of cache size under the standard LRU replacement policy. This information can be used to schedule jobs or to
doi:10.1109/hpca.2002.995703
dblp:conf/hpca/SuhDR02
fatcat:mjpy5jpsejfkbchaz6gakyifqy