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Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003.
This paper presents a full System-on-Chip (SoC) design flow from system specification to RT-level. A new approach to obtain a full path to implementation for SoC design is proposed. This approach combines architecture design space exploration using the VCC design environment and system synthesis using the ROSES design flow, allowing a true and complete system level design flow. The experiment with a VDSL application shows a significant reduction of design time. Abstract architecturedoi:10.1109/aspdac.2003.1195020 fatcat:65y5optnizby5puls5c66ejewe