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Charge recycling for power reduction in FPGA interconnect
2013
2013 23rd International Conference on Field programmable Logic and Applications
We propose charge recycling (CR) to reduce power consumption in FPGAs. We take advantage of the property that many routing conductors are left unused in any FPGA implementation of an application. Charge recycling via the unused conductors reduces the amount of charge drawn from the supply, lowering energy consumption. We present a routing switch that operates in two modes: normal and CR, and describe the CAD tool changes needed to support CR at the routing and post-routing stages of the flow.
doi:10.1109/fpl.2013.6645509
dblp:conf/fpl/HudaAT13
fatcat:a3jnpbmcqbctfd4hntibv7fii4