Charge recycling for power reduction in FPGA interconnect

Safeen Huda, Jason Anderson, Hirotaka Tamura
2013 2013 23rd International Conference on Field programmable Logic and Applications  
We propose charge recycling (CR) to reduce power consumption in FPGAs. We take advantage of the property that many routing conductors are left unused in any FPGA implementation of an application. Charge recycling via the unused conductors reduces the amount of charge drawn from the supply, lowering energy consumption. We present a routing switch that operates in two modes: normal and CR, and describe the CAD tool changes needed to support CR at the routing and post-routing stages of the flow.
more » ... sults show that dynamic power in the FPGA interconnect can be reduced by up to ∼15-18.4% by the proposed techniques, depending on the performance constraints. 978-1-4799-0004-6/13/$31.00 ©2013 IEEE CLB CB CB SB CLB CB CB SB CLB CB CB SB CLB CB CB SB Routing Wires (a) Top level organization of CLBs, CBs, SBs, and routing wires. VDD Routing Conductor
doi:10.1109/fpl.2013.6645509 dblp:conf/fpl/HudaAT13 fatcat:a3jnpbmcqbctfd4hntibv7fii4