To cite this article: Mariko Hayashi et al 2018 Jpn. J. Appl. Phys. 57 04FR15 View the article online for updates and enhancements. Related content Accurate evaluation of fast threshold voltage shift for SiC MOS devices under various gate bias stress conditions Mitsuru Sometani, Mitsuo Okamoto, Tetsuo Hatakeyama et al. -Threshold-voltage instability in 4H-SiC MOSFETs with nitrided gate oxide revealed by non-relaxation method Mitsuru Sometani, Dai Okamoto, Shinsuke Harada et al. -Evaluation

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... d of threshold voltage shift of SiC MOSFETs under negative gate bias using n-type SiC MOS capacitors Teruyuki Ohashi and Ryosuke Iijima -This content was downloaded from IP address 207.241.231.81 on 25/07 We demonstrated a fast-capacitance-voltage (CV) method for the evaluation of the number and location of holes trapped in a 4H-SiC MOS device under negative gate bias stress. The number of trapped holes was carefully estimated by suppressing recombination and detrapping during stress relaxation. It was found that a large number of holes trapped in a short stress time were reduced by nitridation, and that the hole trapping in a longstress-time region was accelerated by increases in temperature and electric field for a stress. From the results, we determined the respective model for hole trapping and detrapping.