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When integrating software threads together to boost performance on a processor with instruction-level parallel processing support, it is rarely clear which code regions should be aligned and integrated, and which regions should be left alone. This problem grows even worse on a modern VLIW DSP due to complicating factors in both the hardware and compiler: software pipelining, predication, branch delay slots, load delay slots and limited resources. As a result, finding an effective integrationdoi:10.1145/1176760.1176764 dblp:conf/cases/SoD06 fatcat:j7xkib5u25ehvjdwx2jwme5uty