A 24 GHz low power low phase noise dual-mode phase locked loop frequency synthesizer for 60 GHz applications

Nagarajan Mahalingam, Yisheng Wang, Kaixue Ma, Kiat Seng Yeo, Shou Xian Mou
2014 2014 IEEE MTT-S International Microwave Symposium (IMS2014)  
This paper presents a dual-mode PLL synthesizer used in 60 GHz transceiver supporting both IEEE 802.Had and IEEE 802.IS.3c standards with low power consumption and low phase noise. Fabricated in commercial 0.18 11m SiGe BieMOS process and operated with a single 1.8 V supply, the PLL synthesizer provides output frequencies from 22.5 GHz to 26.:3 GHz with phase noise better than -99.5 dBclHz at 1 MHz offset In both the integer and fractional modes of operation. The PLL synthesizer consumes low
more » ... er of only 42 mW and occupies an area of 1.7 mm x 0.8 mm. Index Terms -24 GHz, 60 GHz, dual-mode, frequency synthesizer, fractional-N, integer-N, phase locked loop (PLL).
doi:10.1109/mwsym.2014.6848405 fatcat:tm7qjweounbqtjgpmo6d52azzy