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Control Loop Feedback Mechanism for Generic Array Logic Chip Multiprocessor
[article]
2014
arXiv
pre-print
Control Loop Feedback Mechanism for Generic Array Logic Chip Multiprocessor is presented. The approach is based on control-loop feedback mechanism to maximize the efficiency on exploiting available resources such as CPU time, operating frequency, etc. Each Processing Element (PE) in the architecture is equipped with a frequency scaling module responsible for tuning the frequency of processors at run-time according to the application requirements. We show that generic array logic Chip
arXiv:1402.5617v1
fatcat:z4rsuiuxzzc6dpts5x7i6itp7i