VHDL (Very High Speed Integrated Circuits Hardware Description Language) is one of the most popular languages (IEEE standard) for building software models of hardware systems. While the typical VHDL-based design environment provides tools for code simulation and logic synthesis, no support is given in order to cope with the increasing complexity of VHDL descriptions and the widespread demand for their quality evaluation and improvement. Automated source code analysis is a valuable approach to

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... velop, measure and compare models in order to assure the satisfaction of quality requirements of VHDL descriptions before adding them to model libraries. Therefore a static analyzer may assist the user in the challenging task of introducing significant modifications and improvements into source code so that, assuring that VHDL code is developed according to some well-founded guidelines, a relevant impact on the quality of the overall design process may be achieved. The goal of this paper is to summarize the activities carried out within the SAVE project, leading to the development of a collection of quality analysis tools in order to improve modifiability, reusability, readability of models reducing the VHDL descriptions complexity. S. Bologna et al. (eds.), Achieving Quality in Software