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This thesis deals with the designing of CMOS image sensors with in-pixel analog-to-digital conversion. A 2-stage memory write scheme for Pulse-Width-Modulation digital pixel sensors is proposed. It utilizes the characteristics of Gray-code counters and partitions a single data write operation into two separated write operations such that the size of the in-pixel memory can be significantly reduced. A Pulse-Frequency-Modulation pixel significantly reduces the integration time without sacrificingdoi:10.32920/ryerson.14653755.v1 fatcat:fslukmns6jbwxmcsovxqizacgm