Harmony: static noise analysis of deep submicron digital integrated circuits

K.L. Shepard, V. Narayanan, R. Rose
1999 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of very large scale integrated (VLSI) systems. A metric for noise immunity is defined, and a static noise analysis methodology based on this noise-stability metric is introduced to demonstrate how noise can be analyzed systematically on a full-chip basis using simulationbased transistor-level analysis. We then describe Harmony,
more » ... two-level (macro and global) hierarchical implementation of static noise analysis. At the macro level, simplified interconnect models and timing assumptions guide efficient analysis. The global level involves a careful combination of static noise analysis, static timing analysis, and detailed interconnect macromodels based on reduced-order modeling techniques. We describe how the interconnect macromodels are practically employed to perform coupling analysis and how timing constraints can be used to limit pessimism in the analysis. Index Terms-Deep-submicron IC's, interconnect coupling, signal integrity, static noise analysis.
doi:10.1109/43.775633 fatcat:nldan4e2ezaxna2s6vy46bw4ja