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Early wire characterization for predictable network-on-chip global interconnects
2007
Proceedings of the 2007 international workshop on System level interconnect prediction - SLIP '07
This work envisions a common design methodology, applicable for every interconnect level and based on early wire characterization, to provide a faster convergence to a feasible and robust design. We claim that such a novel design methodology is vital for upcoming nanometer technologies, where increased variations in both device characteristics and interconnect parameters introduce tedious design closure problems. The proposed methodology has been successfully applied to the wire synthesis of a
doi:10.1145/1231956.1231969
dblp:conf/slip/HatirnazBPLMAM07
fatcat:t6v6g2qnk5be3i3ywm3uwxpwdm