A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is
Traditionally placement evaluation metrics have been based on wirelength and congestion measures and are independent of the logic network topology. However, the actual timing measure, which is used in a design closure loop, is path-based and dependent on the network topology. In this paper, we propose a designtopology aware metric that encapsulates the structural property of the circuit and physical goodness of the given placement. We present such a metric which is based on path monotonicitydoi:10.1145/764808.764857 dblp:conf/glvlsi/RamjiD03 fatcat:lmwhryl2rzcw5nwqbqu4ilodu4