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The design and integration challenges for SOCs include DFT for test integration to meet the test quality and test cost goals. This paper describes the DFT implementation on TNETD7300, a single chip ADSL modem SOC with analog and digital sub-systems, IP cores and embedded memories, to address several test optimisation requirements, including scan architecture support for high-end and low-cost testers, concurrent test of digital logic with analog functions, at-speed testing for logic operating indoi:10.1109/test.2004.1387340 dblp:conf/itc/NikilaP04 fatcat:smtyugbryfgozjphwawdwzf2au