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Transpose-free variable-size FFT accelerator based on-chip SRAM
2014
IEICE Electronics Express
This paper presents a transpose-free variable-size fast fourier transform (FFT) accelerator on a digital signal processing (DSP) chip. Several parallel schemes are utilized to calculate a batch of smallsize FFT algorithms to achieve high performance and throughput. For middle-and large-size of FFT, we propose a transpose-free Cooley-Tukey scheme that uses the random access feature of on-chip SRAM memory to avoid the DDR access of matrix with column-wise and improves the utilization of DDR
doi:10.1587/elex.11.20140171
fatcat:h6ygih5gxnb73cd4p5iczwpidm