Two-phase synchronization with sub-cycle latency

Rostislav (Reuven) Dobkin, Ran Ginosar
<span title="">2009</span> <i title="Elsevier BV"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/nxrpampd2jc5lizkp7v3ahze74" style="color: black;">Integration</a> </i> &nbsp;
Synchronizers typically incur long latency of multiple-clock cycles, resulting in low throughput. This paper presents two novel fast synchronizers, both based on two-phase protocols: a two-flip-flop synchronizer which reduces the data cycle from 6-12 down to 2-4 clock cycles, and a LDL synchronizer which strives for maximum throughput and 'sub-cycle latency,' namely data transfers that incur no extra penalty due to synchronization. These synchronizers are useful for data transfers over long
more &raquo; ... rconnects. Simulations of best-and worst-case scenarios are presented which demonstrate the improved performance of the novel synchronizers. The results are compared to two-clock FIFO and to conventional two-flip-flop synchronizers.
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