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Robust DC and efficient time-domain fast fault simulation
Purpose -Imperfactions in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, "golden", design of an electronic circuit. By fault simulation one simulates all situations. Normally this leads to a large list of simulations in which for each defect a steady-state (DC) solution is determined followed by a transient simulation. We improve the robustness and the effciency of these simulations. Design/methodology/approach -Determining the DC solution can bedoi:10.1108/compel-12-2012-0364 fatcat:zrcted4dl5e7bavduai3rxrkra