um excelente orientador, que com muita paciência me mostrou o caminho correto a seguir, transmitindo segurança e muito conhecimento para o desenvolvimento deste trabalho. Aos meus professores do IFSP, Ricardo Pires, Alexandre Brincalepe Campo, Omar Alves e Luiz Carlos Moreira, por terem acreditado no meu potencial e me incentivado a cursar o mestrado. Ao Dr. Marius Strum e aos demais colegas do GSEIS, em especial a Edgar Leonardo Romero, que muito me ajudou com sua experiência, Raul Acosta, que

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... além de amigo foi um professor, e cujo trabalho foi fundamental para o desenvolvimento da minha pesquisa. Também a Joel Muñoz, que não mediu esforços para me ajudar com este trabalho. Ao meu amigo Mário Raffo, que ingressou comigo no mestrado e me acompanhou em todos os passos, inclusive nas matérias cursadas e no tema da pesquisa. Esta amizade rendeu muitos frutos para este trabalho. A meus pais, que me apoiaram em cada decisão e ajudaram a traçar o caminho que chegou a esse mestrado. Tudo que consegui na minha vida devo a eles. A minha namorada Leila, que acompanhou lado a lado por todos estes anos e me fez crescer como pessoa. Me apoiou durante todo o mestrado e foi muito compreensiva. É minha constante inspiração. Aos meus amigos, Felipe Gambier Santos Souza, José Antonio de Melo Neto e Raniel Victor Machado, que também me deram seu apoio e de alguma forma me ajudaram com meu trabalho. Ao PNM -CNPq, pelo apoio financeiro para a realização deste trabalho. ABSTRACT Support Vector Machines have been largely used in different applications, due to their high classifying capability without errors (generalization capability) and the advantage of not depending on the initial conditions. Among the developed algorithms for the SVM training, the Sequential Minimal Optimization (SMO) is one of the fastest and the one of the most efficient algorithms for executing this task. Important dedicated hardware implementations of the training phase of the SVM have been proposed for digital FPGA. Most of them are very restricted about the quantity of input samples to be trained due to the fact that they implement numeric solutions. Only two works with implementation in the SMO algorithm for the SVM training in hardware have been reported recently, and just one is able to train an important quantity of input samples, however it is restricted for only one specific benchmark. In the last decade, with the technology based on static memory (SRAM), FPGAs has provided a unique aspect of flexibility: the capability of dynamic reconfiguration, which involves altering the programmed design at run-time and allows area's saving. In addition, although leading to some time penalty, the execution time is still faster when compared with purely software solutions. In this work we present a totally hardware general-purpose implementation of the SMO algorithm. In this general-purpose approach, training of examples with different number of samples and elements are possible, and, motivated by the sequential nature of some of the SMO tasks, a dynamically reconfigurable architecture is developed. A study of the general-purpose implementation with fixed-point codification is presented, as well as the quantization effects. The architecture is implemented in the Xilinx Virtex-IV XC4VLX25 device, and timing and area data are provided. Synthesis details are exploited. A simulation using dynamic circuit switching is carried out in order to validate the system's dynamic reconfiguration aspects. The architecture was tested in the training of three different benchmarks; the training on the reconfigurable hardware was accelerated up to 30 times when compared with software solution, and studies points to an area saving up to 22.38% depending on the synthesis and implementation methodologies adopted in the project. .