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A novel switched-RC sampling MDAC is proposed to obtain high linearity under low-voltage and low-power conditions without significant degradation in speed or causing any reliability problem. Moreover, the proposed MDAC has the capability of working as the front-end stage of a pipelined ADC while its front-end S/H stage has been removed to save power consumption. The proposed techniques have been employed to design a 10-bit 100 MSample/s ADC with 1 V p−p,diff input signal in a 90 nm CMOS processdoi:10.1587/elex.5.67 fatcat:c5umc7sqvbct7dje44gowkubve