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A CMOS-compatible plasmonic waveguide with a metal or metal-like strip sandwiched in-between dielectrics has been proposed for intra-chip communication in the more-than-Moore era. A sequence of numerical models has been presented to evaluate the plasmonic waveguide performance. For device-level consideration, we demonstrated through simulations that Cu (1450 nm pitch) and PLD-TiN (900 nm pitch) plasmonic waveguides symmetrically sandwiched by SiO2 with much smaller and hence denserdoi:10.1109/jphot.2020.3024119 fatcat:ozxivytjvrdrvdqctgoczm7wjy