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Proceedings of the 27th annual international symposium on Computer architecture - ISCA '00
Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimaera, a prototype system that integrates a small and fast reconfigurable functional unit (RFU) into the pipeline of an aggressive, dynamically−scheduled superscalar processor. Chimaera is capable of performing 9−input/1−output operations on integer data. We discuss the Chimaera C compiler that automatically mapsdoi:10.1145/339647.339687 fatcat:bzisrdfvsfhobg7wte7y3vibce