Nanowire systems: technology and design

P.-E. Gaillardon, L. G. Amaru, S. Bobba, M. De Marchi, D. Sacchetto, G. De Micheli
2014 Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences  
Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this study, we consider double independent gate, vertically stacked nanowire field effect transistors (FETs) with gate-allaround structures and typical diameter of 20 nm. These devices, which we have successfully fabricated and evaluated, control the ambipolar behaviour of the nanostructure by selectively enabling one type of carriers. These transistors work as switches with electrically programmable polarity
more » ... d thus realize an exclusive or operation. The intrinsic higher expressive power of these FETs, when compared with standard complementary metal oxide semiconductor technology, enables us to realize more efficient logic gates, which we organize as tiles to realize nanowire systems by regular arrays. This article surveys both the technology for double independent gate FETs as well as physical and logic design tools to realize digital systems with this fabrication technology. on September 21, 2017 Downloaded from Phil. Trans. R. Soc. A 372: 20130102 approaches to very-large-scale system-on-chip (SoC) design stems from the physical limitations and the costs of current manufacturing technologies and from the desire to use more efficient devices, still within the realm of silicon manufacturing. The downscaling of the physical features of field-effect transistors (FETs) has successfully produced better and cheaper devices. Nevertheless, current semiconductor technologies have succeeded mainly along two avenues: fully depleted silicon on insulator [1] and FinFET [2,3] technologies. The latter (also called TriGate technology) is a major departure from planar semiconductor manufacturing: better transistor charge control is achieved at the price of a more complex three-dimensional fabrication process. Within the quest of future technologies, we describe here vertically stacked silicon nanowire field effect transistors (SiNWFETs) [4] as a promising extension to the FinFETs. An SiNW is a thin wire of silicon material, with a diameter ranging from some nanometres to some tenths of nanometres. Transistors are formed by surrounding a segment of the wire by an insulator (such as SiO 2 or HfO 2 ) and then by a coaxial conducting material (gate), thus forming a so-called gate-all-around (GAA) transistor. This structure yields an excellent electrostatic control of the transistor channel, consisting of the nanowire itself under the gate. As a measurable result, the transistor gives a higher I on /I off ratio (i.e. current ratio of the conducting over non-conducting device) [5] . At advanced technology nodes, an increasingly larger number of devices are affected by Schottky contacts at the source and drain interfaces. Hence, devices face an ambipolar behaviour, i.e. each device exhibits n-and p-type characteristics simultaneously because of the possible flow of electrons and holes in the channel. This phenomenon is often suppressed in most technologies because of the desire to create unipolar transistors, i.e. devices with a specific type of carriers: electrons for n-type and holes for p-type transistors. Nevertheless, an important recent breakthrough has shown [6,7] that it is of high interest to control the ambipolar phenomenon through programmable polarity devices. Indeed, by engineering the source and drain contacts and by constructing independent double-gate (DG) structures, the device polarity can be electrostatically programmed to be either n-or p-type at run time. The functionality of a transistor with controllable polarity is an exclusive or (EXOR) of the logic signals on both gates. Thus, the fundamental switching primitive, the DG-SiNWFET, is intrinsically more expressive in terms of logic when compared with standard complementary metal oxide semiconductor (CMOS) transistors. In other words, while regular transistors act as switches, the DG-SiNWFETs act as comparators. The potential advantage of this powerful logic primitive may be offset by the interconnect complexity. This trend is not a surprise for nanosystems in general, including scaled CMOS. Regularity is one of the key features to increase the yield of integrated circuits at advanced technology nodes [8], while keeping the routing complexity under control. Therefore, nanowire systems can be realized as regular arrays of elementary logic blocks, called sea of tiles (SoT) [9] . Thanks to a novel symbolic layout methodology, a desired logic function can be mapped onto an array of logic tiles, thereby enabling the automatic placement of digital circuits onto a SoT organization. In a similar vein, a logic design has to be mapped efficiently onto the SiNW primitives. These primitives can support the realization of both unate and binate functions. Note that CMOS logic primitives are inherently inverting, thus privileging the realization of negative unate functions. Hence, logic synthesis and algorithms supporting the mapping of architectural-level specification into DG-SiNWFET netlists are mandatory. This paper aims at surveying the main results associated with DG-SiNWFETs from technology to physical design and to logic synthesis. The remainder of the paper is organized as follows. In §2, we present our DG-SiNWFET technology and its circuit-level features. In §3, we introduce means of describing regular transistor arrangements to mitigate the impact of the additional gate, and summarize the associated physical design methodology. In §4, we describe the basis for a new logic synthesis flow, whereas, in §5, we derive the potential of the approach for arithmetic and fault-tolerant architectures. Section 6 concludes this work. on September 21, 2017 Downloaded from
doi:10.1098/rsta.2013.0102 pmid:24567471 pmcid:PMC3928901 fatcat:a2vzyrsexjcutiy7t3xgzaml3q