Digital and analog TFET circuits: Design and benchmark

S. Strangio, F. Settino, P. Palestri, M. Lanuzza, F. Crupi, D. Esseni, L. Selmi
2018 Solid-State Electronics  
Digital and analog TFET circuits: Design and benchmark / Strangio, S.; Settino, F.; Palestri, P.; Lanuzza, M.; Crupi, F.; Esseni, D.; Selmi, L. Abstract In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of
more » ... rcuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10 nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral finFETs and the same static power. In spite of the asymmetry between p-and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDD lower than 0.4V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions. After the initial report in [1], complementary-metal-oxide-semiconductor (CMOS) transistors based on band-to-bandtunneling (BtBT), usually referred to as Tunnel-FETs (TFETs), have been extensively explored as possible replacements of, or complements to, conventional MOSFETs for low-power/low-energy electronic circuits targeting a supply voltage VDD below 0.5 V [2][3][4] [5]. TFETs embody a promising small slope FET concept able to achieve a subthreshold swing (SS) below the 60 © 2018. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0/ The final publication is available at: https://doi.org/10.1016/j.sse.2018.05.003 mV/dec room temperature limit of conventional MOSFETs, as demonstrated by many theoretical works based on simulations (see [5] and references therein), and by some recent encouraging experimental results [6] [7] . The lower SS compared to a conventional MOSFET can be exploited in two ways: if the threshold voltage is the same as in the MOSFET, the TFET will have a lower off-current (and thus lower static energy dissipation); if instead the same off-current is set in both devices, the TFET will be able to deliver a similar on-current as the MOSFET at a lower supply voltage VDD, thus reducing both static and dynamic energy dissipations (which are proportional to VDD and VDD 2 , respectively). In this respect, circuit simulations have attributed to TFETs the potential to outperform conventional MOSFETs in the ultra-low voltage domain (VDD < 0.4 V) in both analog [8][9][10] and digital [11][12][13][14][15][16][17] applications. At higher supply voltages, however, the drive current of TFETs is significantly lower than the one of conventional MOSFETs. It is thus clear that TFETs can outperform MOSFETs only if they can deliver an SS significantly smaller than 60 mV/dec over a large current range in the subthreshold region. In many experiments this target has not been achieved, which may be due to fundamental as well as to material and device design issues [18][19][20][21][22][23][24]. As a result, the performance of the fabricated TFETs lags behind the optimistic figures reported in simulation studies, but experimental results have been steadily improving along the years. Another intrinsic advantage of TFETs over conventional MOSFETs stems from the lower temperature dependence of BtBT compared to thermionic emission [56], which may directly translate in less temperature sensitivity of TFET circuits. This has not been observed in early experimental reports about TFETs mainly because the conduction at very low current levels was often dominated by Trap-Assisted-Tunneling (TAT) and Shockley-Read-Hall (SRH) recombination processes [25]. Nevertheless, the fabrication process for TFETs is also getting more and more controlled and encouraging variability analysis are being reported both for statistically meaningful experimental samples [26], and for simulation based studies [27][28]. Among the possible technological platforms, silicon/silicon-germanium TFETs have the advantage of easy integration with mainstream CMOS [25][26][29][30]. However, the achieved performance is not very rewarding, especially for n-type TFETs, due to fundamental limit set by the indirect band-gap. As opposite to Si-based devices, TFETs based on heterojunction III-V structures are more promising [6][7][31] [32] since they take advantage on their direct (and smaller) energy gap, and in fact they have shown higher on-current as well as SS below 60 mV/dec in the low current range. In addition, III-Vs provide more degrees of freedom for creating hetero-junctions and reduce ambipolar behavior. The on-current and SS value are not the only important parameters to assess the possible advantages of TFETs against MOSFETs. TFETs are known to have a higher gate-drain capacitance [33], which can result in a switching time penalty compared to MOSFETs due to the Miller effect. On the other hand, the output conductance is lower due to the different electrostatics compared to MOSFETs [8]. Consequently, it is very important and timely to analyze the possible employment of TFETs in relevant benchmarking circuits. The fabrication processes for TFETs are however not as mature as for conventional CMOS transistors, and there exist very few reports about fabrication of TFET circuits (inverters in [25][34], current mirrors in © 2018. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0/ The final publication is available at: https://doi.org/10.1016/j.sse.2018.05.003 [35], half-SRAM cell in [36]), in many cases employing transistors that are not at the state-of-the-art of TFETs and are based on silicon platforms. To assess the possible advantages of TFETs versus advanced CMOS transistors in realistic circuits, many simulation works have been presented. Most of such efforts have been devoted to digital circuits. SRAMs, for example, have been analyzed by various authors using different models for the TFETs either calibrated against experimental silicon devices [37] or obtained from full-quantum simulations [38]. Various SRAM topologies to circumvent the unidirectional conduction and/or to improve the cell stability have been also proposed [39][40][41][42][43][44][45][46]. Full-adders have been analyzed in [47][48][49] using lookup-tables (LUTs) obtained from TCAD simulations and calibrated against full-quantum results for hetero-junction complementary TFETs [50]. Level shifters have been also recently addressed in [50][51]. As for analog circuits, an operational transconductance amplifier (OTA) has been studied in [52], while a 6-bit successive approximation register (SAR) ADC has been simulated in [53] considering complementary double-gate GaSb-InAs heterojunction TFETs. A thorough investigation in [54] analyzed mm-wave low noise amplifiers, oscillators, mixers, rectifiers and detectors using Verilog-A models for the hetero-junction GaSb-InAs TFETs presented in [55]. OTAs, current mirrors and trackand-old circuits based on InAs and GaSb/InAs TFETs have been analyzed in [8] using LUTs built from TCAD simulations calibrated on the device characteristics of [28][32]. Basic analog building blocks (current mirrors, differential pairs, diodeconnected transistors) have been simulated in [56] using compact models calibrated on experimental strained silicon TFETs, proposing the deployment of TFETs in niche applications exploiting the lower temperature sensitivity. The performance of track and hold and comparators based on complementary heterojunction TFETs has been assessed in [9]. Different topologies of TFET-based power management circuits for energy harvesting applications have been proposed in [10][57]. Low-dropout linear voltage regulators with III-V TFETs have been analyzed in [58]. In most of these works, the characteristics of the p-TFETs are obtained by mirroring the ones of the n-TFETs. In this paper, we present a comparison between aggressively scaled template heterojunction TFETs and FinFETs considering a wide variety of digital and analog/mixed-signal building blocks. The characteristics of the TFETs have been derived from fullquantum simulations [59], where n-TFETs and p-TFETs have been separately designed and have their own individual characteristics. This work reviews and extends previous publications from our group [9][37][47][48][51] by using the same set of devices for a large variety of circuits and supply voltages, and drawing more general conclusions. Furthermore, differently from the previous papers, the comparison with silicon FinFETs is carried-out at fixed occupied area and absolute off-current, hence essentially at the same static power. The paper proceeds as follows. The devices and the simulation methodology are described in Section 2. Simulation results for digital building blocks such as inverters, full-adders, SRAM cells and level shifters are reported in Section 3. Analog/mixed-© 2018. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0/ The final publication is available at: https://doi.org/10.1016/j.sse.2018.05.003 signal building blocks (op-amps, current mirrors and comparators) are analyzed in Section 4. Conclusions are drawn in Section 5.
doi:10.1016/j.sse.2018.05.003 fatcat:ptppcp6mancw7glfdwpvaiyoem