2.3 An Energy-Efficient Configurable Lattice Cryptography Processor for the Quantum-Secure Internet of Things

Utsav Banerjee, Abhishek Pathak, Anantha P. Chandrakasan
2019 2019 IEEE International Solid- State Circuits Conference - (ISSCC)  
This paper presents a configurable lattice cryptography processor which enables quantum-resistant security protocols for IoT. Efficient sampling architectures, coupled with a low-power SHA-3 core, provide two orders of magnitude energy savings over software. A single-port RAM-based NTT architecture is proposed, which provides ~124k-gate area savings. This is the first ASIC implementation which demonstrates multiple lattice-based protocols proposed for NIST post-quantum standardization.
doi:10.1109/isscc.2019.8662528 dblp:conf/isscc/BanerjeePC19 fatcat:vb3vp7o7n5f3riofdxpee6bkci