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An Analysis of U.S. Patent #5,243,538 "Comparison and Verification System for Logic Circuits and Method Thereof"
On Sept. 7, 1993, U. S. Patent Number 5,243,538 was awarded to four Hitachi employees for a technique for comparing logic circuits using Binary Decision Diagrams (BDDs). Although the U. S. patent application was filed on Aug. 7, 1990, they had filed for a patent in Japan on Aug. 9, 1989, and hence this earlier date should be used in determining the prior art. The key property exploited by the patentees is that by generating the BDDs for the two logic circuits according to a unique ordering ofdoi:10.1184/r1/6603188 fatcat:o6dwushnxzcbldcqmlrakrpn5m