Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment

O. Semenov, H. Sarbishaei, M. Sachdev
Sixth International Symposium on Quality of Electronic Design (ISQED'05)  
As technology feature size is reduced, ESD becomes one of the dominant failure modes due to the lower gate oxide breakdown voltage. Also, the holding voltage of LVTSCR devices is reduced with operating temperature increase. As a result, during stress testing (burn-in), the risk of latch-up in LVTSCR is extremely high. In this paper, a new latch-up free LVTSCR-based protection circuit is proposed. It can be reliably used in sub-0.18 um CMOS technologies and burnin environment. The proposed ESD
more » ... rcuit has higher holding voltage by 1.5X than the conventional LVTSCR structure at burn-in temperature. Under 3kV HBM ESD stress, the developed LVTSCR-based protection circuit has the voltage peak less than the conventional LVTSCR structure and GG-MOSFET by 2X and 1.25X, respectively.
doi:10.1109/isqed.2005.17 dblp:conf/isqed/SemenovSS05 fatcat:tqbatwhgurhr7kshu46znaxl5y