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As cache hierarchies become deeper and the number of cores on a chip increases, managing caches becomes more important for performance and energy. However, current hardware cache management policies do not always adapt optimally to the applications behavior: e.g., caches may be polluted by data structures whose locality cannot be captured by the caches, and producer-consumer communication incurs multiple round trips of coherence messages per cache line transferred. We propose load and storedoi:10.1145/2503210.2503224 dblp:conf/sc/ParkYKHK13 fatcat:yvtqvwtg3rbnbcfgdbamqq5dy4