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A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding
2008
2008 IEEE International Symposium on Circuits and Systems
This paper describes a sub 100-mW H.264/AVC MP@L4.1 integer-pel motion estimation processor core for a low power video encoder. It supports macro block adaptive frame field (MBAFF) encoding and bi-directional prediction for a resolution of 1920 × 1080 pixels at 30 fps which haven't been realized by conventional methods[1][2]. The proposed processor core features a novel hierarchical algorithm, a reconfigurable ring-connected systolic array architecture, and a segmentationfree rectangle-access
doi:10.1109/iscas.2008.4541551
dblp:conf/iscas/MurachiMMHIIYLKKY08
fatcat:amjzntjg6vhqzigrknv7z32hea