A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding

Yuichiro Murachi, Kosuke Mizuno, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto
2008 2008 IEEE International Symposium on Circuits and Systems  
This paper describes a sub 100-mW H.264/AVC MP@L4.1 integer-pel motion estimation processor core for a low power video encoder. It supports macro block adaptive frame field (MBAFF) encoding and bi-directional prediction for a resolution of 1920 × 1080 pixels at 30 fps which haven't been realized by conventional methods[1][2]. The proposed processor core features a novel hierarchical algorithm, a reconfigurable ring-connected systolic array architecture, and a segmentationfree rectangle-access
more » ... arch window buffer. The processor core has been designed in a 90 nm CMOS technology, and its core size is 2.5 × 2.5 mm 2 . With one core, one reference frame can be handled, and 48 mW is consumed at 1 V. Two-core configuration dissipates 96 mW for two reference frames.
doi:10.1109/iscas.2008.4541551 dblp:conf/iscas/MurachiMMHIIYLKKY08 fatcat:amjzntjg6vhqzigrknv7z32hea