Trace table based approach for pipelined microprocessor verification [chapter]

Jun Sawada, Warren A. Hunt
1997 Lecture Notes in Computer Science  
This paper presents several techniques for formally verifying pipellned microprocessor implementations that contain out-of-order execution and dynamic resolution of data-dependent hazards. Our principal technique models the trace of executed instructions using a tablebased representation called a MAETT. We express invariant properties of pipefined implemenLations by specifying relations between fields in the MAETT. To show the viabifity of this technique, we have proved the correctness of a
more » ... le out-of-order completion pipetined microprocessor design using the ACL2 theorem prover. This verification was performed incrementally by proving that the specified relations hold for all microarchitectural states reachable from a flushed implementation state, eventually permitting us to prove that the entire pipelined machine design implements its ISA specification.
doi:10.1007/3-540-63166-6_36 fatcat:lrycriyst5aotf5bgyljirz6ja