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Update-based cache coherence protocols for scalable shared-memory multiprocessors
1994
Proceedings of the Twenty-Seventh Hawaii International Conference on System Sciences HICSS-94
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In this paper, two hardware-controlled update-based cache coherence protocols are presented. The paper discusses the two major disadvantages of the update protocols: inefficiency of updates and the mismatch between the granularity of synchronization and the data transfer. The paper presents two enhancements to the update-based protocols, a write combining scheme and a finer grain synchronization, to overcome these disadvantages. The results demonstrate the effectiveness of these enhancements
doi:10.1109/hicss.1994.323135
fatcat:eacn4ubhefbu3ncko4dputmmv4