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Lecture Notes in Electrical Engineering
For the design of complex systems, formal modeling languages such as UML or SysML find significant attention. The typical model-driven design flow assumes thereby an initial (abstract) model which is iteratively refined to a more precise description. During this process, new errors and inconsistencies might be introduced. In this paper, we propose an automatic method for verifying the consistency of refinements in UML or SysML. For this purpose, a theoretical foundation is considered from whichdoi:10.1007/978-3-319-24457-0_1 fatcat:n2ixrocmlnandcvra5lhhww2wu