Automatic Refinement Checking for Formal System Models [chapter]

Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler
2015 Lecture Notes in Electrical Engineering  
For the design of complex systems, formal modeling languages such as UML or SysML find significant attention. The typical model-driven design flow assumes thereby an initial (abstract) model which is iteratively refined to a more precise description. During this process, new errors and inconsistencies might be introduced. In this paper, we propose an automatic method for verifying the consistency of refinements in UML or SysML. For this purpose, a theoretical foundation is considered from which
more » ... the corresponding proof obligations are determined. Afterwards, they are encoded as an instance of Satisfiability Modulo Theories (SMT) and solved using proper solving engines. The practical use of the proposed method is demonstrated and compared to a previously proposed approach.
doi:10.1007/978-3-319-24457-0_1 fatcat:n2ixrocmlnandcvra5lhhww2wu