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In this project, novel circuits for FULL ADDER are proposed using new XOR or XNOR gates. The conventional design of XOR or XNOR gates shows that the not gate in the schematic has drawbacks. So by investigating advanced XOR or XNOR gates we proposed the schematic design. The proposed schematics are optimized in terms of speed, delay, power and power delay product. We developed six novel hybrid full adder schematics based on exploring new XOR or XNOR gates. Each designed schematics have theirdoi:10.22214/ijraset.2021.35286 fatcat:hl4chwahh5awnp57yt25aaossu