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Viser: providing serializability in hardware with simplified cache coherence
2015
Companion Proceedings of the 2015 ACM SIGPLAN International Conference on Systems, Programming, Languages and Applications: Software for Humanity - SPLASH Companion 2015
While existing architectures like x86 and SPARC provide strong hardware memory consistency models, such as TSO, programming language memory models are more relaxed. This divide nullifies the usefulness of providing strong hardware memory models, since languages and compilers provide a weaker guarantee. Moreover, current shared memory systems implement complex cache coherence protocols which add to the complexity. This work proposes a microarchitecture, called Viser, that ensures strong
doi:10.1145/2814189.2815375
dblp:conf/oopsla/Biswas15
fatcat:jwvxznfazne6rcj6o3tfm73wgu