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A 400-MIPS/200-MFLOPS (peak) custom 64-b VLSI CPU chip is described. The chip is fabricated in a 0.75pm CMOS technology utilizing three levels of metalization and optimized for 3.3-V operation. The die size is 16.8 mm X 13.9 mm and contains 1.68M transistors. The chip includes separate 8-kilobyte instruction and data caches and a fully pipelined floating-point unit (FPU) that can handle both IEEE and VAX standard floating-point data types. It is designed to execute two instructions per cycledoi:10.1109/4.165336 fatcat:zugbyrtgobdzvdiyotfuck5huq