A 200-MHz 64-b dual-issue CMOS microprocessor

D.W. Dobberpuhl, R.T. Witek, R. Allmon, R. Anglin, D. Bertucci, S. Britton, L. Chao, R.A. Conrad, D.E. Dever, B. Gieseke, S.M.N. Hassoun, G.W. Hoeppner (+11 others)
1992 IEEE Journal of Solid-State Circuits  
A 400-MIPS/200-MFLOPS (peak) custom 64-b VLSI CPU chip is described. The chip is fabricated in a 0.75pm CMOS technology utilizing three levels of metalization and optimized for 3.3-V operation. The die size is 16.8 mm X 13.9 mm and contains 1.68M transistors. The chip includes separate 8-kilobyte instruction and data caches and a fully pipelined floating-point unit (FPU) that can handle both IEEE and VAX standard floating-point data types. It is designed to execute two instructions per cycle
more » ... ng scoreboarded integer, floatingpoint, address, and branch execution units. Power dissipation is 30 W at 200-MHz operation.
doi:10.1109/4.165336 fatcat:zugbyrtgobdzvdiyotfuck5huq