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Crosstalk Fault Tolerant Processor Architecture - A Power Aware Design
Second IEEE International Workshop on Electronic Design, Test and Applications
The advent of DSM technology and multi-GHz operation of processors has increased the severity of cross-talk faults. Even with many preventive solutions like cross-talk driven routing, power supply shielding and intentional skewing; cross-talk faults cannot be completely avoided. In this paper we present an enhanced power aware fault tolerant pipelined architecture -xIDAC/E. In our earlier work -IDAC/E, compression and encoding were done on individual instructions whereas xIDAC/E operates on
doi:10.1109/delta.2004.10067
dblp:conf/delta/VenkateswaranKRSSBMR04
fatcat:hrtcrgwtcrf5pecvct25z3jiua