Crosstalk Fault Tolerant Processor Architecture - A Power Aware Design

N. Venkateswaran, V.B. Kumar, R. Raghavan, R. Srinivas, S. Subramanian, V. Balaji, V. Mahalingam, T.L. Rajaprabhu
Second IEEE International Workshop on Electronic Design, Test and Applications  
The advent of DSM technology and multi-GHz operation of processors has increased the severity of cross-talk faults. Even with many preventive solutions like cross-talk driven routing, power supply shielding and intentional skewing; cross-talk faults cannot be completely avoided. In this paper we present an enhanced power aware fault tolerant pipelined architecture -xIDAC/E. In our earlier work -IDAC/E, compression and encoding were done on individual instructions whereas xIDAC/E operates on
more » ... C/E operates on grouped instruction partitions. This offers higher compression efficiency due to repeatability and power reduction due to lesser memory accesses. Simulation results are provided with regard to instruction partitioning, their compression & encoding, and memory re-fetches. Analysis show this power reduction overcompensate the overheads due to partitioning, compression and encoding. The impact of encoding of address & data bus on fault tolerance and power is also provided.
doi:10.1109/delta.2004.10067 dblp:conf/delta/VenkateswaranKRSSBMR04 fatcat:hrtcrgwtcrf5pecvct25z3jiua