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<i title="International Journal for Research in Applied Science and Engineering Technology (IJRASET)">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/hsp44774azcezeyiq4kuzpfh5a" style="color: black;">International Journal for Research in Applied Science and Engineering Technology</a>
A network on a chip is a network based communication subsystem on an integrated circuit, most typically between modules in a system on chip (SoC). The modules on the IC are typically semiconductor IP cores schematizing various functions of the computer system and are designed to be modular in the sense of network science. The network on chip is a switching network between SOC in the router. Deadlock and Livelock freedom in Routing is one of current issue in NoC routing. The Deadlock and<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.22214/ijraset.2020.5129">doi:10.22214/ijraset.2020.5129</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/uva2os4oyjehxm4j252uxg4vhm">fatcat:uva2os4oyjehxm4j252uxg4vhm</a> </span>
more »... freedom prohibiting certain routing turns. NOC based architecture uses great amount of power. To schedule the processes, a round-robin scheduler generally allocate time for sharing, giving each job based on time slot (its allowance of CPU time) and interrupts the duty if it's not completed by them. When the duty is resumed next time a time slot is assigned to it. If the process ends or changes its state to waiting during its fixed time quantum, the scheduler selects the primary process within the ready queue to execute. In the absence of time sharing, or if the quantum were large relative to the size of the role, a process that produced large jobs would be preferred over other processes. Round-robin algorithm is a pre algorithm technique as the scheduler forces the process out of the CPU once the time allocation expires. Round robin algorithm reduces the dynamic power in the module. The algorithm is written by using Verilog HDL and tested on Xilinx 14.7 ISE and the algorithm is implemented by using FPGA VERTEX5 kit.
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