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Memory controllers for high-performance and real-time MPSoCs
2011
Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '11
Designing memory controllers for complex real-time and highperformance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must be provided in a reliable manner at low cost and with low power consumption. This special session contains four presentations that describe these challenges and proposed solutions for DRAM and flash memory controllers, respectively. The first presentation discusses performance and reliability issues in flash memories,
doi:10.1145/2039370.2039374
dblp:conf/codes/AkessonHCDGCKVW11
fatcat:bbujgrkoirchtgd6qign64st2m