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Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interference and degrade overall performance. One technique to reduce the interconnect traffic is to co-locate threads that share data on the same processor. Multiple threads sharing in the cache should reduce compulsory and invalidation misses, thereby improving execution time. To test this hypothesis, we compared a variety ofdoi:10.1109/isca.1994.288151 dblp:conf/isca/ThekkathE94 fatcat:xi5zgrlg5bfcjhu2j5syri6zfy